The present invention relates to a process for electroplating fine geometry electrically conductive features between dielectric features photolithographically patterned in a layer of a fully-imidized photosensitive polyimide dielectric composition, particularly to a method for reducing the formation of distortions in the electrically conductive features formed by the electroplating step.
Continual advancements in the speed and integration level of integrated circuits used in high performance systems have created a demand for the development of an interconnect technology that offers a high wiring density, good electrical characteristics for the propagation of high speed signals, and good thermal performance. Multi-layer interconnection schemes with fine line conductors and associated ground planes have been proposed for applications in high performance systems. Fine geometry copper conductor lines defined in a photolithographically patterned layer of a low-dielectric constant polymer, such as a polyimide, have emerged as a versatile packaging approach for the conductive interconnection lines between densely packed integrated circuit chips in high performance systems.
In general, fine geometry electrically conductive features, such as conductor lines, can be produced by the following steps: (1) depositing a thin layer of a metallic seed layer on a dielectric substrate, (2) etching the seed layer to form fine geometry lines that serve as the electroplating base for the conductor lines, (3) spin coating a layer of a photosensitive dielectric composition over the dielectric substrate and etched seed layer, (4) photolithographically patterning the layer of the dielectric composition to form fine geometry dielectric features, the seed layer being uncovered between these dielectric features, and (5) electroplating an electrically conductive material between the patterned dielectric features onto the metallic seed layer to form electrically conductive features.
The formation of distortions in the electrically conductive features that are electroplated between the patterned dielectric features is undesirable because of the nonreproducible electrical characteristics these distortions introduce into the conductive features. For example, when the surfaces of the conductive features are rough, the electrical resistance is unpredictable. Also, nodular film growth on the surface of the conductive features increases the risk of electrical short circuits between adjacent conductive features. As the speed and integration level of integrated circuits in high performance systems increases, there is an increasing need to reduce, and preferably prevent, the formation of distortions in the densely packed electrically conductive features that interconnect the integrated circuits.